1. Field of the Disclosure
The present disclosure relates to a liquid crystal display (LCD), and more particularly, to a thin film transistor array substrate and a method for manufacturing the thin film transistor array.
2. Discussion of the Related Art
With the progress of information-dependent society, the demand for various display devices has increased. To meet such a demand, efforts have been made to develop flat panel display devices such as liquid crystal display (LCD) devices, plasma display panels (PDPs), electro-luminescent display (ELD) devices, vacuum fluorescent display (VFD) devices, and the like. Some types of such flat panel display devices are being applied to various devices and/or appliances for display purposes.
LCDs have been used as a substitute for cathode ray tubes (CRTs) in association with mobile image display devices because LCDs have advantages of superior picture quality, light weight, thinness, and low power consumption. Various applications of LCDs are being developed in association with not only mobile image display devices such as monitors of notebook computers, but also monitors of televisions to receive and display broadcasting signals. Successful application of LCDs to various image display devices depends on whether or not the LCDs can produce desired high picture quality including high resolution, high brightness, and large display area, while maintaining its desired characteristics of lightness, thinness, and low power consumption.
LCDs have a structure including a first substrate and a second substrate joined together in such a manner that a space is established between the first and second substrates. A liquid crystal layer is sealed in the space between the first and second substrates. The first substrate includes a plurality of gate lines arranged in one direction while being uniformly spaced apart from one another. A plurality of data lines are arranged in a direction perpendicular to the gate lines while being uniformly spaced apart from one another. The crossing of the data lines and the gate lines define pixel regions P. The first substrate also includes a plurality of pixel electrodes formed at respective pixel regions P, and a plurality of thin film transistors (TFTs) T each formed at an intersection between one of the gate lines and one of the data lines. A data signal on each data line is applied to one of the pixel electrodes in response to a signal applied to one of the gate lines.
Although not shown, the second substrate may include a black matrix layer for blocking incident light to regions other than the pixel regions P. The second substrate may also include R, G, and B color filter layers formed at a region corresponding to each pixel region P, and configured to reproduce color tones. A common electrode may be disposed on the color filter layers, and configured to reproduce an image.
In the above-described LCD, the liquid crystals of the liquid crystal layer arranged between the first and second substrates in each pixel region may be oriented in a certain direction by an electric field generated between the pixel electrode and the common electrode. The amount of light passing through the liquid crystal layer is controlled based on the orientation of the liquid crystal layer, in order to appropriately represent an image.
An LCD having the above-mentioned driving principle is called a twisted nematic (TN) mode LCD. In addition to such a TN mode LCD, an in-plane switching (IPS) mode LCD has been developed which uses a horizontal electric field. In the IPS mode LCD, a pixel electrode and a common electrode are formed on a first substrate at each pixel region of the first substrate such that the pixel electrode and common electrode extend parallel to each other, in order to generate an in-plane electric field (horizontal field). The liquid crystal layer may be oriented in a certain direction by the in-plane electric field.
The structures of TFTs formed at intersections between gate lines and data lines on a first substrate and pixel electrodes formed at pixel regions in LCDs as described above, and the processes for forming the TFTs and pixel electrodes will be described in association with FIGS. 1 and 2. FIG. 1 is a sectional view illustrating a TFT array substrate according to the related art. FIG. 2 is a flow chart illustrating a method for manufacturing a TFT array substrate according to the related art.
As shown in FIG. 1, each TFT of the thin film transistor array substrate includes a gate electrode 11 disposed, such that it is protruded from the gate line (not shown). A semiconductor layer 13 is disposed in the form of an island above the gate electrode 11 such that a gate insulating layer 12 is disposed between the gate electrode 11 and the semiconductor layer 13. Each TFT also includes a source electrode 14a and a drain electrode 14b respectively disposed at opposite sides of the semiconductor layer 13 while being spaced apart from each other. The source electrode 14a is formed to be protruding from the data line (not shown). The semiconductor layer 13 may have a laminated structure including a lower amorphous silicon layer 13a, and an upper impurity layer (n+ layer) 13b disposed on the amorphous silicon layer 13a except for a channel region. The impurity layer 13b is in contact with lower surfaces of the source electrode 14a and drain electrode 14b. 
A pixel electrode 16 is disposed such that it is in contact with a portion of an upper surface of the drain electrode 14b in each TFT. A passivation layer 15 is formed, as an interlayer, between the pixel electrode 16 and each of the source electrode 14a and drain electrode 14b. The above-described structure formed on the first substrate 10 is referred to as a “TFT array”. A method for manufacturing the TFT array will be described in conjunction with one TFT with reference to FIG. 2. FIG. 2 is a flow chart showing a process for manufacturing a TFT array according to the related art.
As shown in FIG. 1 and FIG. 2, a metal layer is deposited over the first substrate 10, and is then selectively removed to form a gate line and a gate electrode 11 such that the gate electrode 11 is protruded from the gate line as in block 11S. Thereafter, a gate insulating layer 12 is deposited over the upper surface of the first substrate 10 including the gate electrode 11.
Subsequently, a semiconductor layer 13 and a metal layer are sequentially disposed on the upper surface of the gate insulating layer 12, and are then selectively removed to form a data line (not shown) and source and drain electrodes 14a and 14b as in block 12S. The semiconductor layer 13 has a laminated structure including a lower amorphous silicon layer 13a, and an upper impurity layer 13b. Since the semiconductor layer 13 is disposed beneath the source and drain electrodes 14a and 14b, it is patterned together with the metal layer upon the formation of the source and drain electrodes 14a and 14b. The region defined between the source and drain regions 14a and 14b is selectively subjected to a diffractive light exposure process such that the metal layer and the impurity layer 13b of the semiconductor layer 13 are removed from the region. The remaining portion of the semiconductor layer 13 is defined as a channel region.
A passivation layer 15 is then disposed on the upper surface of the gate insulating layer 12 including the data line, source electrode 14a and drain electrode 14b. A passivation layer hole is then formed to expose a portion of an upper surface of the drain electrode 14b as in block 13S. Thereafter, a transparent electrode material is deposited over the entire upper surface of the passivation layer 15 such that the passivation layer hole is buried by the transparent electrode material. The transparent electrode material may then be selectively removed to form a pixel electrode 16 in a pixel region as in block 14S.
However, the above-mentioned TFT array substrate according to the related art may have certain drawbacks. In order to form the TFT array substrate and a TFT transistor array on the TFT array substrate, it may be necessary to use at least four masks for the formation of the gate lines, the formation of the semiconductor layer and data lines, the formation of the passivation layer holes, and the formation of the pixel electrodes.
Such masks used to pattern desired films are expensive. Furthermore, every time a mask is used, it is necessary to perform various processes such as deposition of a film to be patterned, coating of a photoresist film, light exposure, development of the photoresist film, and etching of the film using the developed photoresist film. After completion of the etching process, it is also necessary to perform additional processes such as cleaning. For this reason, the use of masks incurs an increase in costs, an increase in processing time, and a degradation in productivity.